620 Ingenieurwissenschaften und Maschinenbau
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A level graph G = (V,E,λ) is a graph with a mapping λ : V → {1,...,k}, k ≥ 1, that partitions the vertex set V as V = V1 ∪...∪ Vk, Vj = λ-1(j), Vi ∩ Vj = ∅ for i ≠ j, such that λ(v) = λ(u) + 1 for each edge (u, v) ∈ E. Thus a level planar graph can be drawn with the vertices of every Vj, 1 ≤ j ≤ k, placed on a horizontal line, representing the level lj , and without crossings of edges, which can be drawn as straight line segments between the levels. Healy, Kuusik and Leipert gave a complete characterization of minimal forbidden subgraphs for level planar graphs (MLNP patterns) for hierarchies [4]. Minimal in terms of deleting an ar- bitrary edge leads to level planarity. A radial graph partitions the vertex set on radii, which can be pictured as concentric circles, instead of levels, lj = (j cos(α), j sin(α)), α ∈ [0,2π), mapped around a shared center, where j, 1 ≤ j ≤ k indicates the concentric circles’ radius. Comparing embeddings of radial graphs with that of level graphs we gain a further possibility to place an edge and eventually avoid edge crossings which we wish to prevent for planarity reasons. This offers a new set of minimal radial non planar subgraphs (MRNP patterns). Some of the MLNP pat- terns can be adopted as MRNP patterns while some turn out to be radial planar. But based on the radial planar MLNP patterns and the use of augmentation we can build additional MRNP patterns that did not occur in the level case. Furthermore we point out a new upper bound for the number of edges of radial planar graphs. It depends on the subgraphs in- duced between two radii. Because of the MRNP patterns these subgraphs can either consist of a forest or a cycle with several branches. Applying the bound we are able to characterize extremal radial planar graphs. Keywords: radial graphs, minimal non-planarity, extremal radial planar
For audio signals, we use the sign of the coefficients of the redundant discrete wavelet transform to generate primary hash vectors assigning bit 1 to positive or zero coefficients and bit 0 in the negative case. Discarding the highest frequency band and using a 6 step transform we get for each sample a 6 bit primary hash value which we may save as an integer. We then select a possible primary hash value (in our experiments we chose 0 or 63) and take the time indices where this primary hash value occurs as the secondary hash vector which is attributed to the whole audio signal. Comparing two audio signals, the number of elements in the intersection of the corresponding time indices are called "number of matches", a high number may indicate a similarity between the files. This secondary hash vector turns out to be robust against addition of noise, GSM-, G.726-, MP3 coding and packet loss. It may therefore be useful to detect spam telephone calls without analyzing the semantic content by the similarity of the corresponding signals. An algorithm is given to detect similar but shifted signals. Results of experiments are reported using a test corpus of 5 000 audio files of regular calls and 200 audio files of different versions of 20 original spam recordings augmented by a set of 45 files of different versions of 9 "special spam" signals.
The objective of this paper is to implement a baseband OFDM transceiver on FPGA hardware. The design uses 8-point SLT/ISLT (Slantlet/Inverse Slantlet) for the processing module with processing block of 8 inputs data wide. All modules are designed and implemented using VHDL programming language. Software tools used in this work includes Altera Quartus II 7.2 and ModelSim Altera 6.1g, to assist the design process and downloading process into FPGA board while Cyclone III board EP3C120F780C7 is used to realize the designed module.
This paper presents the design procedure and implementation results of a proposed software defined radio (SDR) using Altera Cyclone II family board. The implementation uses Matlab/SimulinkTM, Embedded MatlabTM blocks, and Cyclone II development and educational board. The design has first implemented in Matlab/SimulinkTM environment. It is then converted to VHDL level using Simulink HDL coder. The design is synthesized and fitted with Quartus II 9.0 Web Edition® software, and downloaded to Altera Cyclone II board. The results show that it is easy to develop and understand the implementation of SDR using programmable logic tools. The paper also presents an efficient design flow of the procedure followed to obtain VHDL netlists that can be downloaded to FPGA boards.
Die Grundlage für diese Arbeit ist das opensource Roboterkettenfahrzeug SRV1 der Firma Surveyor [www-surveyor]. Im Auslieferungszustand ist es möglich, das Fahrzeug über ein Steuerungsprogramm fernzusteuern. Dies entspricht dem Funktionsumfang eines normalen ferngesteuerten Fahrzeugs, erweitert um eine Kamera, jedoch ohne jegliche Autonomie oder Intelligenz. Da das Fahrzeug auf einem embedded Board aufgebaut ist, welches über eine WLAN Verbindung verfügt, bietet es einen guten Ausgangspunkt für Erweiterungen. Ziel dieser Arbeit ist es eine Grundlage für autonome Fahrten zu schaffen. Als Betriebssystem wird uClinux, ein Linux für embedded Plattformen genutzt. Das Fahrzeug soll um einen zur Orientierung dienenden Kompass erweitert werden. Außerdem kommt ein RFID-Reader zum Einsatz, mit dessen Hilfe werden RFID-Transponder auf einer Teststrecke als künstliche Landmarken zur Positionsbestimmung genutzt. Es wird eine Software für autonome Fahrten entwickelt, die es ermöglicht, durch Verwendung der erweiterten Hardware, den Roboter eigenständig Punkte der Teststrecke anfahren zu lassen. Hierzu ist es erst notwendig alle Hardware im Betriebssystem, beispielsweise durch Treiber verfügbar zu machen.